1. Field of Invention
The present invention relates to a shift register circuit including a plurality of stages connected in a cascaded fashion, a driving circuit for driving an electrooptical device including a plurality of pixels, an electrooptical device using such a driving circuit, and an electronic apparatus employing such an electrooptical device as a display device.
2. Description of Related Art
A conventional electrooptical device, such as an active matrix liquid crystal display device, consists mainly of a device substrate on which pixel electrodes together with switching elements are formed in a matrix fashion, an opposite substrate on which a color filter is formed, and a liquid crystal disposed in a space between the two substrates. In this structure, if a scanning signal (selection voltage) is applied to a switching element via a scanning line, the switching element is brought into a conductive state. When the switching element is in the conductive state, if an image signal is applied to a pixel electrode via a data line, an arbitrary charge is stored in the liquid crystal layer between that pixel electrode and an opposite electrode (common electrode). After storing the charge, a non-selection voltage is applied to the switching element so as to turn it off. If the liquid crystal layer has a sufficiently high resistance, the charge is maintained in the liquid crystal layer even after the switching element has been turned off. The orientation of the liquid crystal can be controlled for each pixel by controlling the amount of charge stored via the respective switching elements. Thus, desired information can be displayed.
In this technique, the operation of storing the charge into the liquid crystal layer for each pixel is required only in a particular period. This allows the liquid crystal display device to be driven in a time division multiplexing fashion in which scanning lines and data lines are used in common for a plurality of pixels, as described below. That is, first, the scanning lines are sequentially selected by a scanning line driving circuit. Second, during a selection period in which one scanning line is selected, one or more data lines are selected by a data line driving circuit. Third, a sampled image signal is applied to the selected data line(s).
The scanning line driving circuit and the data line driving circuit are generally similar in construction to each other. For example, in a typical construction as shown in FIG. 19, the data line driving circuit includes a shift register circuit 1560 consisting of a plurality of unit circuits connected in a cascade fashion. A transfer start pulse DX is applied to the shift register circuit 1560 at the start of each horizontal scanning period. The transfer start pulse DX is transferred through the cascaded unit circuits from one to another in response to a clock signal CLX and an inverted clock signal CLXINV, and sampling pulses S1-Sn to be used to sample a data signal are output one after another from the unit circuits. Similarly, in a typical scanning line driving circuit, a transfer start pulse DY is applied, instead of the transfer start pulse DX, to a shift register circuit at the start of each vertical scanning period, and instead of the clock signal CLX and the inverted clock signal CLXINV, a clock signal CLY and an inverted clock signal DLYINV are supplied every horizontal period.
In the case of an active matrix liquid crystal display device including switching elements each formed of thin film transistors (TFTs) and also including a built-in driving circuit formed of TFTs for driving the switching elements, a rather high voltage of about 12 V is required as the operating voltage. As a result, a similar voltage is also required for the scanning line driving circuit and the data line driving circuit which perform logic operations in synchronization with clock signals. In contrast, a timing generator (not shown in FIG. 19) for supplying clock signals to a liquid crystal display panel is generally formed of a CMOS circuit whose output voltage is about 3 to 5 V. To handle the voltage difference, the data line driving circuit 158 includes, as shown in FIG. 19, level shifters (level conversion circuits) 1512 and 1522 as clock interfaces disposed at the input stage to convert a signal with a small logic swing of 0 to 3 V to a signal with a large logic swing of 0 to 12 V. That is, in the conventional scanning line driving circuit and data line driving circuit, the signal with the small logic swing generated by the timing generator is supplied to the unit circuits of the shift register circuit 1560 after being converted by the level shifter into a signal with the large logic swing.
In recent years, electrooptical devices, in particular active matrix liquid crystal display devices widely used in portable electronic apparatuses, are required to operate with very low power consumption. Of various circuits in the electrooptical device, the data line driving circuit 158 operates in synchronization with a highest-frequency clock signal and needs the greatest power consumption. Therefore, a key point to reduce the power consumption of the electrooptical device is to reduce the power consumption of the data line driving circuit 158.
In the conventional data line driving circuit 158 described above, the clock signal CLX and the inverted clock signal CLXINV level-shifted by the level shifters 1512 and 1522 are supplied to the unit circuits at the respective stages of the shift register circuit 1560. However, in this technique, the lines A and B which the clock signals with the large logic swing are supplied tend to become long. As a result, the capacitance associated with the lines A and B becomes large.
In general, electric power consumed by a capacitive load increases in proportion to the capacitance C of the capacitor, the frequency f of a signal supplied to the capacitor, and the square of the voltage V of the signal. Because the lines A and B serve to transmit the clock signals with the large logic swing along a large distance, the lines A and B have large capacitance C, and large voltages V are applied to the large capacitance C. Therefore, large electric power is consumed when the clock signals with the large logic swing are applied to the capacitance associated with the lines A and B.
In view of the above, it is one aspect of the present invention to provide a shift register circuit applicable to a data line driving circuit and capable of operating with small power consumption, a driving circuit using such a shift register circuit for driving an electrooptical device, an electrooptical device, and an electronic apparatus using the electrooptical device as a display device.
According to an aspect of the invention, there is provided a shift register circuit including a plurality of stages connected in a cascaded fashion for sequentially transferring an input signal in response to a clock signal with a large amplitude. The shift register circuit may further include a plurality of level shifting circuits each coupled with one or more stages of the shift register circuit, each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with each level shifting circuit.
In this shift register circuit constructed in the above-described manner, each level shifting circuit coupled with one or more stages of the shift register circuit supplies a level-shifted clock signal with the large amplitude to the one or more stages coupled with that level shifting circuit. This allows a reduction in the length of lines used to supply the clock signal with the large amplitude compared with the conventional technique in which the clock signal with the large amplitude is supplied by one level shifting circuit to all stages. As a result, the capacitance associated with the lines used to supplying the clock signal with the large amplitude becomes small, and thus the power consumption due to the capacitance decreases.
On the other hand, in this technique, the length of the lines used to supply the clock signal with the small amplitude to the respective level shifting circuit becomes long. However, because the amplitude of the signal supplied via those lines is small, the power consumption due to the capacitance of these lines is much smaller than that associated with the large-amplitude lines.
In the present invention, the respective stages of the shift register circuit are preferably formed such that the input signal may be transferred in both directions. This allows the selecting direction to be changed depending on the application. More specifically, if this shift register circuit is employed in a horizontal or vertical scanning circuit of a display device, it becomes possible to display an image in a horizontally or vertically inverted fashion.
Furthermore, in the shift register circuit according to the present invention, it is desirable that one enabling circuit be provided for each level shifting circuit. Each enabling circuit enables the corresponding level shifting circuit to operate immediately before, or at the same time, as one or more stages of the shift register circuit coupled with that corresponding level shifting circuit, start of transferring the input signal. Each enabling circuit also disables the corresponding level shifting circuit to operate immediately after, or at the same time, as the one or more stages of the shift register circuit coupled with that corresponding level shifting circuit, complete the transferring of the input signal. In this construction, only the level shifting circuit which is required to operate, is enabled to operate, and the other level shifting circuit are disabled. As a result, unnecessary operations of the level shifting circuit are prevented, and thus power consumed by the level shifting circuit is minimized.
Preferably, each enabling circuit is a latch circuit which latches a first signal in response to a clock signal with a large amplitude supplied to a stage located ahead of the one or more stages of the shift register circuit coupled with each level shifting circuit, and which latches a second signal in response to a clock signal with a large amplitude supplied to a stage located behind the one or more stages of the shift register circuit coupled with that level shifting circuit, thereby enabling and disabling the level shifting circuit by the latched signals. Alternatively, each enabling circuit may be a logic circuit which determines the logical OR of the output signal of a stage located ahead of the one or more stages coupled with the level shifting circuit, the output signal of the one or more stages coupled with the level shifting circuit, and the output signal of a stage located behind the one or more stages coupled with the level shifting circuit, thereby enabling or disabling the level shifting circuit to operate in accordance with the output signal of the logic circuit.
In the case where such an enabling circuit is provided, it is desirable that the level shifting circuit include a shutting-off circuit for shutting off the power to the level circuit or shutting off the clock signal with the small amplitude applied to the level shifting circuit when the level shifting circuit is disabled by the enabling circuit, thereby preventing the level shifting circuit from consuming unnecessary power.
Furthermore, in the present invention, it is desirable that the shift register circuit and the level shifting circuit be formed on the same single substrate. Furthermore, it is desirable that the shift register circuit and the level shifting circuit be formed of thin film transistors formed on the same single substrate using the same process. By integrating various parts in the above-described manner, it becomes possible to reduce the total cost of the driving circuit and also reduce the space required to install the driving circuit. In particular, when thin film transistors are employed as the transistors forming the shift register circuit, if the level shifting circuit is also formed of thin film transistors on the same substrate using the same process, then the both circuits have similar electric characteristics, such as a logical threshold voltage, and thus both circuits can operate in a highly reliable fashion.
According to another aspect of the invention, there is provided a driving circuit for driving an electrooptical device, including a transfer circuit including a plurality of stages connected in a cascaded fashion, for sequentially transferring an input signal in response to a clock signal with a large amplitude and a plurality of level shifting circuits each coupled with one or more stages of the transfer circuit, each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with each level shifting circuit.
According to still another aspect of the invention, there is provided a driving circuit for driving an electrooptical device including pixels disposed at locations corresponding to respective intersections between a plurality of scanning lines and a plurality of data lines. The driving circuit serves to drive the above pixels and may include a scanning line driving circuit for sequentially selecting the scanning lines, and a data line driving circuit including a transfer circuit that includes a plurality of stages connected in a cascaded fashion for transferring an input signal in response to a clock signal with a large amplitude. The data line driving circuit serves to sequentially select the data lines on a line-by-line or group-by-group basis in response to the transferring of the input signal performed by the transfer circuit. Each group includes a plurality of data lines, and a plurality of level shifting circuits. Each level shifting circuit is coupled with one or more stages of the transfer circuit and serves to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with that level shifting circuit. An image signal supplying circuit supplies an image signal to one or more data lines selected by the data line driving circuit.
In the driving circuit constructed in the above-described manner, each level shifting circuit coupled with one or more stages of the transfer circuit including a plurality of stages connected in a cascaded fashion supplies a level-shifted clock signal with the large amplitude to the one or more stages coupled with that level shifting circuit. This allows a reduction in the length of lines used to supply the clock signal with the large amplitude compared with the conventional technique in which the clock signal with the large amplitude is supplied by one level shifting circuit to all stages. This results in a reduction in the capacitance associated with the large-amplitude lines, and thus power consumption due to the capacitance associated with these lines can be reduced.
On the other hand, in this construction, the length of the lines used to supply the clock signal with the small amplitude to the respective level shifting circuit becomes long. However, because the amplitude of the signal supplied via those lines is small, the power consumption due to the capacitance of these lines is much smaller than that associated with the large-amplitude lines.
In this driving circuit according to the present invention, it is desirable that the scanning line driving circuit include at least a transfer circuit including a plurality of stages connected in a cascaded fashion for sequentially transferring an input signal and sequentially selecting the respective scanning lines in response to the transferring of the input signal, and a plurality of level shifting circuits each coupled with one or more stages of the transfer circuit, each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with that level shifting circuit. This construction allows a reduction in the power consumption of the scanning line driving circuit. That is, the reduction in power consumption is achieved not only in the data line driving circuit but also in the scanning line driving circuit.
In this driving circuit according to the present invention, it is desirable that the driving circuit further include an enabling circuit coupled with the corresponding level shifting circuit of the data line driving circuit and/or the scanning line driving circuit, for enabling the corresponding level shifting circuit to operate. The enabling circuit enables the level shifting circuit to operate immediately before or at the same time as one or more stages coupled with that level shifting circuit start transferring the input signal, and the enabling circuit disables that level shifting circuit to operate immediately after or at the same time as the one or more stages coupled with that level shifting circuit complete the transferring of the input signal.
In this construction, only the level shifting circuit which is required to operate is enabled to operate, and the other level shifting circuit are disabled. As a result, unnecessary operations of the level shifting circuit are prevented, and thus power consumed by the level shifting circuit is minimized.
According to still another aspect of the invention, there is provided an electrooptical device including pixels disposed at locations corresponding to respective intersections between a plurality of scanning lines and a plurality of data lines. The electrooptical device may further include a scanning line driving circuit for sequentially selecting the scanning lines, a data line driving circuit including a transfer circuit. The transfer circuit may include a plurality of stages connected in a cascaded fashion for transferring an input signal in response to a clock signal with a large amplitude. The data line driving circuit serves to sequentially select the data lines on a line-by-line or group-by-group basis in response to the transferring of the input signal performed by the transfer circuit, where each group includes a plurality of data lines, a plurality of level shifting circuits each coupled with one or more stages of the transfer circuit, and each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with that level shifting circuit. An image signal supplying circuit for supplies an image signal to one or more data lines selected by the data line driving circuit.
In this driving circuit according to the present invention, it is desirable that the scanning line driving circuit include at least a transfer circuit including a plurality of stages connected in a cascaded fashion for sequentially transferring an input signal and sequentially selecting the respective scanning lines in response to the transferring of the input signal, and a plurality of level shifting circuits each coupled with one or more stages of the transfer circuit, each level shifting circuit serving to convert a clock signal with a small amplitude to a clock signal with a large amplitude and supply the resultant clock signal to the one or more stages coupled with that level shifting circuit.
In this driving circuit according to the present invention, it is desirable that the driving circuit further include an enabling circuit coupled with the corresponding level shifting circuit of the data line driving circuit and/or the scanning line driving circuit, for enabling the corresponding level shifting circuit to operate. The enabling circuit enables the level shifting circuit to operate immediately before or at the same time as one or more stages coupled with that level shifting circuit start transferring the input signal. The enabling circuit disables that level shifting circuit to operate immediately after or at the same time as the one or more stages coupled with that level shifting circuit complete the transferring of the input signal.
The electrooptical device according to the present invention has features and advantages similar to those obtained in the driving circuit described above, the electrooptical device may include a liquid crystal disposed between two substrates, and transistors corresponding to respective pixels. The transistors serve to apply the image signal supplied to the data lines to the corresponding pixels, the transistors and are formed on one of the two substrates. It is desirable that the transfer circuit and the level shifting circuit of the data line driving circuit and/or of the scanning line driving circuit be formed of thin film transistors formed on the one of the two substrates using the same process. By integrating various parts in the above-described manner, it becomes possible to reduce the total cost of the driving circuit and also reduce the space required to install the driving circuit. In particular, when thin film transistors are employed as the transistors forming the shift register circuit, if the level shifting circuit is also formed of thin film transistors on the same substrate using the same process, then the both circuits have similar electric characteristics, such as a logical threshold voltage, and thus both circuits can operate in a highly reliable fashion.
Furthermore, if the transistors of the respective pixels are also formed using the same process, then all circuits formed on the same substrate become capable of operating in a more reliable and stable fashion.
According to still another aspect of the invention, there is provided an electronic apparatus using the above-described electrooptical device as displaying circuit.